Thiago de Oliveira Coura
Lead Engineer
Belo Horizonte
Summary
Proactive and goal-oriented professional with excellent time management and problem-solving skills. Known for reliability and adaptability, able to quickly learn and apply new skills. Committed to leveraging these qualities to drive team success and contribute to the growth of the organization.
Overview
11
11
years of professional experience
36
36
years of post-secondary education
Work History
Lead Engineer
HCL Technologies
Remote
08.2020 - Current
- We develop dual core SoCs with DSP for audio and video demand with a focus on this new era of neural/AI models. I am on my third release on 22nm technology
- All products are from the same business focus family, so they have the same base microarchitecture and the options change based on power profile, video/audio focus, cryptographic features, available communication IPs
- I work as a SoC DV and I am also responsible for the Formal Regression SoC. This includes 5 subsystems, 4 subsystems of M33/M55 (IPC, iCache...) of ARM cores and the latest TDM/I2C communication
- My work covers the entire scope of silicon development under the umbrella of a SoC DV. Initial plan from a business perspective, SoC microarchitecture, the usual development states, PRE_DFT, RTL, UPF, GLS, maybe an occasional ECO and validation team support
- Technology used for verification follows industry standards, UVM, SV, C lang. Tools, scripts, flows are developed and expected as part of the activities. Software vendor changes, report changes, SDF editing that are often in Gigabytes cannot be done without scripts and tricks
- I am very blessed with the team I work with locally here in Brazil and with the client. Communication is good, enthusiastic and occasionally energetic with a focus on solving the problem, never on people
ASIC Design Verification Engineer
Research Institute Eldorado
Campinas
05.2020 - 09.2022
- I worked on many contracts with Embrapii, which is a government accelerator institution
- The first task was to develop the UVM testbench for some blocks in a high-speed optical transceiver
- The second task was to support a SystemVerilog-only testbench for a high-speed X-ray camera using FPGA
- The last one was to take care of the UVM regression of a pacemaker
Product Validation Engineer II
Jasper Design Automation acquired by Cadence Design Systems
Belo Horizonte
01.2014 - 01.2020
- My career at Cadence was important. Although my position there was in Quality Assurance, I wore many hats
- As an application engineer, I had many opportunities to travel on different occasions (which, if you add up all the time spent traveling, was almost a year) to the old Jasper headquarters and on-site with many relevant customers, supporting the application engineers already assigned to the customer (customer point of contact) or when there was space, I worked alone with the customer
- As I said before, I was part of the QA team. I can't tell you how much I learned about software and software development there. I did and implemented a lot of things and was always eager to learn and learn as much as possible about the JasperGold architecture and all the new stuff related to RD. This always helped me find the tricky bugs
- My last role at Cadence was as an associate product manager. Based on my experience from my QA days, I proposed and implemented many automation systems to support the PM and ensure product quality
Education
CI-Brasil Program (UFRGS)
Porto Alegre, Rio Grande Do Sul, Brazil 05.2001 - 07.2012
Master of Science - Electrical Engineering
UFMG
Belo Horizonte, Minas Gerais, Brazil 05.2001 - 07.2011
Microfabrication of CMOS devices -
UNICAMP-CCS
Campinas, Sao Paulo, Brazil01-2009
Bachelor of Science - Physics
UFMG
Belo Horizonte, Minas Gerais, Brazil 05.2001 - 12.2007
Specialization Program - Data Science
UFMG
Belo Horizonte, Minas Gerais, Brazil 05.2001 -
Skills
- Python Programming
- Bash Scripting
- Perl
- TCL Development
- C Development Skills
- SystemVerilog
- UVM
- SVA
- Git
- Mercurial
- Perforce
Timeline
Lead Engineer
HCL Technologies
08.2020 - Current
ASIC Design Verification Engineer
Research Institute Eldorado
05.2020 - 09.2022
Product Validation Engineer II
Jasper Design Automation acquired by Cadence Design Systems
01.2014 - 01.2020
CI-Brasil Program (UFRGS)
05.2001 - 07.2012
Master of Science - Electrical Engineering
UFMG
05.2001 - 07.2011
Bachelor of Science - Physics
UFMG
05.2001 - 12.2007
Specialization Program - Data Science
UFMG
05.2001 -
Microfabrication of CMOS devices -
UNICAMP-CCS
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